1. Field of the Invention
The present invention relates to field effect transistors and, more particularly, to embodiments of a field effect transistor (FET) structure having one or more ohmic body contacts placed relatively close to the active region of the FET, to embodiments of an integrated circuit structure incorporating a plurality of stacked FETs with such ohmic body contacts and to method embodiments for forming these structures.
2. Description of the Related Art
A semiconductor-on-insulator (SOI) field effect transistor (FET) is a FET formed in the semiconductor layer of a semiconductor-on-insulator wafer. Shallow trench isolations (STI) structures extend through the semiconductor layer and isolated the SOI FET from other devices within the semiconductor layer. As with any FET, an SOIFET comprises a channel region positioned between source/drain regions and a gate structure positioned above the channel region. However, depending upon the configuration of the source/drain regions as well as the thickness of the semiconductor layer, the channel region of the SOIFET may be fully depleted (FD) or partially depleted (PD). Specifically, in a FDSOIFET, the depletion layer of the channel region between the source/drain regions encompasses the full thickness of the semiconductor layer. In a PDSOIFET, the depletion layer between the source/drain regions is only located in an upper portion of the semiconductor layer near the top surface.
In a PDSOIFET, the non-depleted portion of the channel region that is between the source/drain regions and below the depletion layer is typically referred to as the body of the FET. If this body is not contacted, it is referred to as a floating body. Since the floating body is not contacted (i.e., not biased), its voltage may vary (e.g., as result of carrier generation and thereby accumulation). Variations in the voltage of the floating body will lead to variations in the threshold voltage (Vt) of the PDSOIFET. Furthermore, such threshold voltage variations can differ between PDSOIFETs at different locations within an electronic circuit and can, thereby degrade the performance of the electronic circuit.
Generally, the body contacts for PDSOIFETs must be ohmic contacts so that the current-voltage (I-V) curve is linear and symmetric and also to avoid snapback. To achieve an ohmic body contact, it is necessary to avoid placing the contact on an area of the device implanted with source/drain dopants or, more particularly, to avoid placing the contact on an area of the device implanted with source/drain extension dopants. This is because an area of the device implanted with such dopants will have an opposite conductivity type than the body of the FET, thereby forming a PN junction which blocks the connection between the contact and the body. In FETs designed for high-voltage applications, a heavily tilted implant process is used to form deep source/drain extension regions and this heavily tilted implant process can impact a relatively large surface area of the substrate. Typically, to accommodate for the heavily tilted source/drain extension implantation process, a relatively wide shallow trench isolation (STI) structure is formed surrounding the active region of the FET and the body contact is formed outside this STI structure. Ground rules may, for example, require that the body contact by separated from the active region of the FET by a distance of 2.0 μm or more. Unfortunately, this solution adds to the area of the wafer consumed by the FET. An alternative solution involves a hybrid STI structure, which allows the body contact to be formed closer to the active region of the FET. However, this solution involves additional processing steps that add to processing time and costs. Therefore, there is a need in art for a FET having one or more ohmic body contacts that can be placed relatively close to the active region of the FET and a method of forming such a FET.